Multilevel Genetic Placement Algorithm for Large-Scale Mixed-Size SOC Designs

With the continued improvement of the nanometer IC technologies, large-scale mixed-size placement becomes a vital problem where there is a significant size variation between building modules and standard cells. Floorplanning techniques are very suitable to pack modules, but do not scale to hundreds of thousands of objects. Multilevel partitioning algorithms rapidly divide the large scale objects into clusters so that the inter connections are minimized. Therefore we propose a new multilevel floorplanning technique in a design flow that efficiently solves the more general placement problem, i.e. large scale designs and large size variations. The proposed flow relies on an arbitrary multilevel partitioner to provide an arbitrary floorplanner or placer with small scale and high-quality partitions. The standard cells within a partition are seen as a soft module. Then geometric relations of modules for each partition are established by floorplanner. Afterward, standard cells are placed by another call to the standard cell placer. This new technique generates valid placements consisting of modules and standard cells without needing extra time to remove possible overlaps. The use of multilevel also further reduces the runtime as well as improves the solution quality. Empirical evaluation on ibm benchmarks shows substantial runtime improvements compared to Qplace, MPG-MS and Capo, as well as wirelength improvements.